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october 2011 doc id 15676 rev 3 1/23 23 ld39100xx ld39100xx12, ld39100xx25 1 a, low quiescent current, low noise voltage regulator features input voltage from 1.5 to 5.5 v ultra low dropout voltage (200 mv typ. at 1 a load) very low quiescent current (20 a typ. at no load, 200 a typ. at 1 a load, 1 a max in off mode) very low noise with no bypass capacitor (30 v rms at v out = 0.8 v) output voltage tolerance: 2.0 % @ 25 c 1 a guaranteed output current wide range of output voltages available on request: 0.8 v to 4.5 v with 100 mv step and adjustable from 0.8 v logic-controlled electronic shutdown stabilized with ce ramic capacitors c out = 1 f internal current and thermal limit dfn6 (3 x 3 mm) package temperature range: - 40 c to 125 c applications printers personal digital assistants (pdas) cordless phones consumer applications description the ld39100xx provides 1 a maximum current from an input voltage ranging from 1.5 v to 5.5 v with a typical dropout voltage of 200 mv. the device is stable due to the use of ceramic capacitors on the input and output. the ultra low drop-voltage, low quiescent current and low noise features make it suitable for low power battery powered applications. power supply rejection is 65 db at low frequencies and starts to roll off at 10 khz. an enable logic control function puts the ld39100xx in shutdown mode, allowing a total current consumption lower than 1 a. the device also includes short-circuit constant current limiting and thermal protection. dfn6 (3 x 3 mm) table 1. device summary part numbers order codes output voltages ld39100xx ld39100pur adj. from 0.8 v ld39100xx12 ld39100pu12r 1.2 v ld39100xx25 LD39100PU25R 2.5 v www.st.com
contents ld39100xx, ld39100xx12, ld39100xx25 2/23 doc id 15676 rev 3 contents 1 circuit schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5 typical performance characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.1 power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.2 enable function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.3 power good function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
ld39100xx, ld39100xx12, ld39100xx25 circuit schematics doc id 15676 rev 3 3/23 1 circuit schematics figure 1. schematic diagram for the ld39100pu current limit thermal protection out gnd opamp in power-good signal pg internal enable in adj en bandgap reference current limit thermal protection out gnd opamp in power-good signal pg internal enable in in adj en bandgap reference figure 2. schematic diagram for the ld39100puxx current limit thermal protection out gnd opamp in power-good signal pg internal enable in nc en bandgap reference r 1 r 2 current limit thermal protection out gnd opamp in power-good signal pg internal enable in in nc en bandgap reference r 1 r 2
pin configuration ld39100xx, ld39100xx12, ld39100xx25 4/23 doc id 15676 rev 3 2 pin configuration figure 3. pin connection (top view) ld39100puxx en gnd pg v in nc v out en gnd pg v in adj v out ld39100pu table 2. pin description symbol pin n function ld39100pu ld39100puxx en 1 1 enable pin logic input: low = shutdown, high = active gnd 2 2 common ground pg 3 3 power good v out 4 4 output voltage adj 5 - adjust pin v in 6 6 input voltage of the ldo nc - 5 not connected gnd exp pad exposed pad must be connected to gnd
ld39100xx, ld39100xx12, ld39100xx25 maximum ratings doc id 15676 rev 3 5/23 3 maximum ratings note: absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditions is not implied. all values are referred to gnd. table 3. absolute maximum ratings symbol parameter value unit v in dc input voltage -0.3 to 7 v v out dc output voltage -0.3 to v in + 0.3 (7 v max) v en enable pin -0.3 to v in + 0.3 (7 v max) v pg power good pin -0.3 to 7 v adj adjust pin 4 v i out output current internally limited p d power dissipation internally limited t stg storage temperature range - 65 to 150 c t op operating junction temperature range - 40 to 125 c table 4. thermal data symbol parameter value unit r thja thermal resistance junction-ambient 55 c/w r thjc thermal resistance junction-case 10 c/w table 5. esd performance symbol parameter test conditions value unit esd esd protection voltage hbm 4 kv mm 0.4 kv
electrical characteristics ld39100xx, ld39100xx12, ld39100xx25 6/23 doc id 15676 rev 3 4 electrical characteristics t j = 25 c, v in = 1.8 v, c in = c out = 1 f, i out = 100 ma, v en = v in , unless otherwise specified. table 6. electrical characteristics for the ld39100pu symbol parameter test conditions min. typ. max. unit v in operating input voltage 1.5 5.5 v v adj v adj accuracy i out =10ma, t j = 25c 784 800 816 mv i out =10ma, -40c ld39100xx, ld39100xx12, ld39100xx25 electrical characteristics doc id 15676 rev 3 7/23 v en enable input logic low v in =1.5v to 5.5v, -40c electrical characteristics ld39100xx, ld39100xx12, ld39100xx25 8/23 doc id 15676 rev 3 t j = 25 c, v in = v out(nom) + 1 v, c in = c out = 1 f, i out = 100 ma, v en = v in , unless otherwise specified. table 7. electrical characteristics for ld39100puxx symbol parameter test conditions min. typ. max. unit v i operating input voltage 1.5 5.5 v v out v out accuracy v out >1.5v, i out =10ma, t j = 25c -2.0 2.0 % v out >1.5v, i out =10ma, -40c 1.5v, -40c ld39100xx, ld39100xx12, ld39100xx25 electrical characteristics doc id 15676 rev 3 9/23 i en enable pin input current v en = v in 0.1 100 na t on turn-on time (4) 30 s t shdn thermal shutdown 160 c hysteresis 20 c out output capacitor capacitance (see typical performance characteristics for stability) 122f 1. all transient values are guarant eed by design, not production tested 2. dropout voltage is the input-to-output voltage difference at whic h the output voltage is 100 mv below its nominal value. this specification does not apply fo r output voltages below 1.5 v 3. pg pin floating 4. turn-on time is time measured bet ween the enable input just exceeding v en high value and the output voltage just reaching 95% of its nominal value table 7. electrical characteristics for ld39100puxx (continued) symbol parameter test conditions min. typ. max. unit
typical performance characteristics ld39100xx, ld39100xx12, ld39100xx25 10/23 doc id 15676 rev 3 5 typical performance characteristics c in = c out = 1 f. figure 4. v adj accuracy figure 5. v out accuracy figure 6. dropout voltage vs. temperature (v out = 2.5 v) figure 7. dropout voltage vs. temperature (v out = 1.5 v) figure 8. dropout voltage vs. output current figure 9. short-circuit current vs. drop voltage 0.74 0.76 0.78 0.8 0.82 0.84 0.86 -50 -25 0 25 50 75 100 125 150 t [c] v adj [v] v in = 1.8 v, v en = v in , i out = 10 ma 0.74 0.76 0.78 0.8 0.82 0.84 0.86 -50 -25 0 25 50 75 100 125 150 t [c] v adj [v] v in = 1.8 v, v en = v in , i out = 10 ma 2.44 2.46 2.48 2.5 2.52 2.54 2.56 -50 -25 0 25 50 75 100 125 150 t [c] v out [v] v in = 3.5 v, v en = v in , i out = 10 ma 2.44 2.46 2.48 2.5 2.52 2.54 2.56 -50 -25 0 25 50 75 100 125 150 t [c] v out [v] v in = 3.5 v, v en = v in , i out = 10 ma 0 50 100 150 200 250 300 350 -50 -25 0 25 50 75 100 125 150 t [c] dropout [mv] v en to v in , v out = 2.5 v, i out = 1 a 0 50 100 150 200 250 300 350 -50 -25 0 25 50 75 100 125 150 t [c] dropout [mv] v en to v in , v out = 2.5 v, i out = 1 a 0 50 100 150 200 250 300 350 400 -50 -25 0 25 50 75 100 125 150 t [c] dropout [mv] v en to v in , v out @ 1.5 v, i out = 1 a 0 50 100 150 200 250 300 350 400 -50 -25 0 25 50 75 100 125 150 t [c] dropout [mv] v en to v in , v out @ 1.5 v, i out = 1 a 0 0.05 0.1 0.15 0.2 0.25 0 200 400 600 800 1000 1200 i out [ma] dropout [v] v out @ 1.5 v v out = 2.5 v v en to v in 0 0.05 0.1 0.15 0.2 0.25 0 200 400 600 800 1000 1200 i out [ma] dropout [v] v out @ 1.5 v v out = 2.5 v v en to v in 0 0.5 1 1.5 2 2.5 3 3.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 vdrop [v] i sc [a] 125 c 85 c 55 c 25 c 0 c -25 c -40 c v in from 0 to 5.5 v, v en to v in , v out = 0.8 v 0 0.5 1 1.5 2 2.5 3 3.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 vdrop [v] i sc [a] 125 c 85 c 55 c 25 c 0 c -25 c -40 c v in from 0 to 5.5 v, v en to v in , v out = 0.8 v
ld39100xx, ld39100xx12, ld39100xx25 typical performance characteristics doc id 15676 rev 3 11/23 figure 10. output voltage vs. input voltage (v out = 0.8 v) figure 11. output voltage vs. input voltage (v out = 2.5 v) figure 12. quiescent current vs. temperature figure 13. v in input current in off mode vs. temperature figure 14. load regulation figure 15. line regulation 0 0.2 0.4 0.6 0.8 1 1.2 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 v in [v] v out [v] 125c 85c 55c 25c 0c -25c -40c v in from 0 to 5.5 v, v en to v in , v out = 0.8 v, i out = 1 a 0 0.2 0.4 0.6 0.8 1 1.2 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 v in [v] v out [v] 125c 85c 55c 25c 0c -25c -40c v in from 0 to 5.5 v, v en to v in , v out = 0.8 v, i out = 1 a 0 0.5 1 1.5 2 2.5 3 00.511.522.533.544.555.56 v in [v] v out [v] 125c 85c 55c 25c 0c -25c -40c v in from 0 to 5 v, v en to v in , v out = 2.5 v, i out = 1a 0 0.5 1 1.5 2 2.5 3 00.511.522.533.544.555.56 v in [v] v out [v] 125c 85c 55c 25c 0c -25c -40c v in from 0 to 5 v, v en to v in , v out = 2.5 v, i out = 1a 0 20 40 60 80 100 120 140 -50 -25 0 25 50 75 100 125 150 t [c] iq [ a] no load i out = 1 a v in = 1.8 v, v en to v in , v out = 2.5 v 0 20 40 60 80 100 120 140 -50 -25 0 25 50 75 100 125 150 t [c] iq [ a] no load i out = 1 a v in = 1.8 v, v en to v in , v out = 2.5 v 0 0.1 0.2 0.3 0.4 0.5 0.6 -50 -25 0 25 50 75 100 125 150 t [c] iq [ a] v in = 3.5 v, v en to gnd, v out = 2.5 v 0 0.1 0.2 0.3 0.4 0.5 0.6 -50 -25 0 25 50 75 100 125 150 t [c] iq [ a] v in = 3.5 v, v en to gnd, v out = 2.5 v -0.015 -0.01 -0.005 0 0.005 0.01 0.015 -50 -25 0 25 50 75 100 125 150 t [c] load [%/ma] v in = 3.5 v, i out = from 10 ma to 1 a, v en =v in , v out = 2.5 v -0.015 -0.01 -0.005 0 0.005 0.01 0.015 -50 -25 0 25 50 75 100 125 150 t [c] load [%/ma] v in = 3.5 v, i out = from 10 ma to 1 a, v en =v in , v out = 2.5 v -0.04 -0.03 -0.02 -0.01 0 0.01 0.02 0.03 0.04 -50 -25 0 25 50 75 100 125 150 t [c] line [%/v] v in = from 1.8 v to 5.5 v, i out = 100 ma, v en = v in , v out = 0.8 v -0.04 -0.03 -0.02 -0.01 0 0.01 0.02 0.03 0.04 -50 -25 0 25 50 75 100 125 150 t [c] line [%/v] v in = from 1.8 v to 5.5 v, i out = 100 ma, v en = v in , v out = 0.8 v
typical performance characteristics ld39100xx, ld39100xx12, ld39100xx25 12/23 doc id 15676 rev 3 figure 16. line regulation figure 17. supply voltage rejection vs. temperature (v out = 0.8 v) figure 18. supply voltage rejection vs. temperature (v out = 2.5 v) figure 19. supply voltage rejection vs. frequency (v out = 0.8 v) figure 20. supply voltage rejection vs. frequency (v out = 2.5 v) figure 21. output noise voltage vs. frequency v in = 1.8 v, v out = 0.8 v, v en = v in -0.04 -0.03 -0.02 -0.01 0 0.01 0.02 0.03 0.04 -50 -25 0 25 50 75 100 125 150 t [c] line [%/v] v in = from 3.5 v to 5.5 v, i out = 100 ma, v en = v in , v out = 2.5 v -0.04 -0.03 -0.02 -0.01 0 0.01 0.02 0.03 0.04 -50 -25 0 25 50 75 100 125 150 t [c] line [%/v] v in = from 3.5 v to 5.5 v, i out = 100 ma, v en = v in , v out = 2.5 v 0 20 40 60 80 100 -50 -25 0 25 50 75 100 125 150 t [c] svr [db] freq.10 khz, i out = 100 ma freq.1 khz, i out = 10 ma v in from 1.7 v to 1.9 v, v en to v in , v out = 0.8 v 0 20 40 60 80 100 -50 -25 0 25 50 75 100 125 150 t [c] svr [db] freq.10 khz, i out = 100 ma freq.1 khz, i out = 10 ma v in from 1.7 v to 1.9 v, v en to v in , v out = 0.8 v 0 20 40 60 80 100 -50 -25 0 25 50 75 100 125 150 t [c] svr [db] freq. = 10 khz, i out = 100 ma freq. = 1 khz, i out = 10 ma v in from 2.9 v to 3.1 v, v en to v in , v out = 2.5 v 0 20 40 60 80 100 -50 -25 0 25 50 75 100 125 150 t [c] svr [db] freq. = 10 khz, i out = 100 ma freq. = 1 khz, i out = 10 ma v in from 2.9 v to 3.1 v, v en to v in , v out = 2.5 v 0 20 40 60 80 100 0 102030405060708090100110 freq [khz] svr [db] i out = 10 ma i out = 100 ma v in from 1.55 v to 2.05 v, v en to v in , v out = 0.8 v 0 20 40 60 80 100 0 102030405060708090100110 freq [khz] svr [db] i out = 10 ma i out = 100 ma v in from 1.55 v to 2.05 v, v en to v in , v out = 0.8 v 0 10 20 30 40 50 60 70 80 90 100 0 102030405060708090100110 freq [khz] svr [db] i out = 10 ma i out = 100 ma v in from 2.9 v to 3.1 v, v en to v in , v out = 2.5 v 0 10 20 30 40 50 60 70 80 90 100 0 102030405060708090100110 freq [khz] svr [db] i out = 10 ma i out = 100 ma v in from 2.9 v to 3.1 v, v en to v in , v out = 2.5 v 0.0 0.5 1.0 1.5 2.0 2.5 1.e+01 1.e+02 1.e+03 1.e+04 1.e+05 f [hz] en [v/sqrt(hz)] a p - iout = 100ma a p - iout = 10ma a p - iout = 1ma a p - iout = 0a
ld39100xx, ld39100xx12, ld39100xx25 typical performance characteristics doc id 15676 rev 3 13/23 figure 22. enable voltage vs. temperature figure 23. load transient (i out = from 10 ma to 1 a) v en = v in =3.5v, v out =0.8v, i out = from10ma to 1a, t r = t f =5 s figure 24. load transient (v out = 0.8 v) figure 25. load transient (v out = 2.5 v) v en = v in =3.5v, v out =0.8v, i out = from100 ma to 1a, t r = t f =5 s v en = v in =3.5v, v out =2.5v, i out = from10 ma to 1a, t r = t f =5 s figure 26. load transient (i out = from 100 ma to 1 a) figure 27. line regulation transient v en = v in =3.5v, v out =2.5v, i out = from100 ma to 1a, t r = t f =5 s v en = v in =1.8 v to 2.3 v, v out = 0.8v, i out =100 ma, t r = t f = 5 s 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 -50 -25 0 25 50 75 100 125 150 t [c] v en [v] high low v in = 5.5 v i out = 100 ma, v out = 0.8 v 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 -50 -25 0 25 50 75 100 125 150 t [c] v en [v] high low v in = 5.5 v i out = 100 ma, v out = 0.8 v i out v out i out v out i out v out i out v out i out v out i out v out i out v out i out v out v in v out v in v out
typical performance characteristics ld39100xx, ld39100xx12, ld39100xx25 14/23 doc id 15676 rev 3 figure 28. startup transient figure 29. enable transient v en = v in = from 0.8 v, v out =0.8 v, i out = 100 ma v en = 0 to 2 v, v out =0.8 v, v in = 3.5 v, i out = 100 ma, t r = 5 s figure 30. esr required for stability with ceramic capacitors (v out = 0.8 v) figure 31. esr required for stability with ceramic capacitors (v out = 2.5 v) v in = v en = from 1.5 v to 5.5 v, v out = 0.8 v, i out = from 1 ma to 1 a v in = v en = from 3.5 v to 5.5 v, v out = 2.5 v, i out = from1 ma to 1 a v in v out v in v out v en v out v en v out 0 0.05 0.1 0.15 0.2 0.25 1 2 3 4 5 6 7 8 9 10111213141516171819202122 c out [f] (nominal value) esr @ 100 khz [ohm] stable zone unstable zone 0 0.05 0.1 0.15 0.2 0.25 12345678910111213141516171819202122 c out [f] (nominal value) esr @ 100khz [ ] 0 0.05 0.1 0.15 0.2 0.25 12345678910111213141516171819202122 c out [f] (nominal value) esr @ 100khz [ ] stable zone unstable zone
ld39100xx, ld39100xx12, ld39100xx25 application information doc id 15676 rev 3 15/23 6 application information the ld39100xx is an ultra low dropout linear regulator. it provides up to 1 a with a low 200 mv dropout. the input voltage range is from 1.5 v to 5.5 v. the device is available in fixed and adjustable output versions. the regulator is equipped with internal protecti on circuitry, such as short-circuit current limiting and thermal protection. the regulator is stable due to ceramic capacitors on the input and the output. the expected values of the input and output ceramic capacitors are from 1 f to 22 f with 1 f typical. the input capacitor must be connected within 0.5 inches of the v in terminal. the output capacitor must also be connected within 0.5 inches of output pin. there is no upper limit to the value of the input capacitor. figure 32 and figure 33 illustrate the typical application schematics: figure 32. typical application circuit for the fixed output version in gnd v in en pg v out v out c out nc 6 1 2 5 4 3 v off on c in ld39100puxx in gnd v in en pg v out v out c out nc 6 1 2 5 4 3 v off on c in ld39100puxx figure 33. typical application circuit for the adjustable version v in gnd v in en off on c in adj pg v out v out c out r 1 r 2 ld39100pu 6 1 2 5 4 3 v in gnd v in en off on c in adj pg v out v out c out r 1 r 2 ld39100pu 6 1 2 5 4 3
application information ld39100xx, ld39100xx12, ld39100xx25 16/23 doc id 15676 rev 3 for the adjustable version, the output voltage can be adjusted from 0.8 v up to the input voltage, minus the voltage drop across the pmos (dropout voltage), by connecting a resistor divider between the adj pin and the output, thus allowing remote voltage sensing. the resistor divider should be selected using the following equation: v out = v adj (1 + r 1 / r 2 ) with v adj = 0.8 v (typ.) it is recommended to use resistors with values in the range of 10 k to 50 k . lower values can also be suitable, but will increase curren t consumption. 6.1 power dissipation an internal thermal feedback loop disables the output voltage if the die temperature rises to approximately 160 c. this feature protects the device from excessive temperature and allows the user to pu sh the limits of the po wer handling capability of a given circuit board without the risk of damaging the device. it is very important to use a good pc board layout to maximize power dissipation. the thermal path for the heat generated by the device is from the die to the copper lead frame through the package leads and exposed pad to the pc board copper. the pc board copper acts as a heat sink. the footprint copper pads should be as wide as possible to spread and dissipate the heat to the surrounding ambient. feed-through vias to the inner or backside copper layers are also useful in improving the overall thermal performance of the device. the power dissipation of the device depends on the input voltage, out put voltage and output current, and is given by: p d = (v in -v out ) i out the junction temperature of the device is: t j_max = t a + r thja x p d where: t j_max is the maximum junction of the die,125 c; t a is the ambient temperature; r thja is the thermal resistance junction-to-ambient. figure 34. power dissipation vs. ambient temperature 0 0.5 1 1.5 2 2.5 3 3.5 -50 -30 -10 10 30 50 70 90 110 130 t a [c] p d [w] 0 0.5 1 1.5 2 2.5 3 3.5 -50 -30 -10 10 30 50 70 90 110 130 t a [c] p d [w]
ld39100xx, ld39100xx12, ld39100xx25 application information doc id 15676 rev 3 17/23 6.2 enable function the ld39100xx features an enable function. wh en the en voltage is higher than 2 v, the device is on, and if it is lower than 0.8 v, th e device is off. in shutdown mode, consumption is lower than 1 a. the en pin does not have an internal pull-up, whic h means that it cannot be left floating if it is not used. 6.3 power good function most applications require a flag showing that the output voltage is in the correct range. the power good threshold depends on the adjust voltage. when the adjust is higher than 0.92*v adj , the power good (pg) pin goes to high impedance. if the adjust is below 0.80*v adj the pg pin goes to low impedance. if the device is functioning well, the power good pin is at high impedance. if the output voltage is fixed using an external or internal resistor divider, the power good threshold is 0.92*v out . the use of the power good function requires an external pull-up resistor, which must be connected between the pg pin and v in or v out . the typical current ca pability of the pg pin is up to 6 ma. the use of a pull-up resistor for pg in the range of 100 k to 1 m is recommended. if the power good function is not used, the pg pin must remain floating.
package mechanical data ld39100xx, ld39100xx12, ld39100xx25 18/23 doc id 15676 rev 3 7 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark.
ld39100xx, ld39100xx12, ld39100xx25 package mechanical data doc id 15676 rev 3 19/23 dim. mm. inch. min. typ. max. min. typ. max. a0. 8 00. 9 0 1.00 0.0 3 1 0.0 3 5 0.0 39 a1 0 0.02 0.05 0 0.001 0.002 a 3 0.20 0.00 8 b 0.2 3 0. 3 00. 38 0.00 9 0.012 0.015 d2. 9 0 3 .00 3 .10 0.114 0.11 8 0.122 d2 2.2 3 2. 38 2.4 8 0.0 88 0.0 9 4 0.0 98 e2. 9 0 3 .00 3 .10 0.114 0.11 8 0.122 e2 1.50 1.65 1.75 0.05 9 0.065 0.06 9 e0. 9 50.0 3 7 l0. 3 0 0.40 0.50 0.012 0.016 0.020 dfn6 ( 3 x 3 mm) mechanical data 7 9 466 3 7a
package mechanical data ld39100xx, ld39100xx12, ld39100xx25 20/23 doc id 15676 rev 3 dim. mm. inch. min. typ. max. min. typ. max. a 33 0 12. 99 2 c 12. 8 1 3 .2 0.504 0.51 9 d 20.2 0.7 9 5 n60 2. 3 62 t1 8 .4 0.724 ao 3 . 3 0.1 3 0 bo 3 . 3 0.1 3 0 ko 1.1 0.04 3 po 4 0.157 p 8 0. 3 15 tape & reel qfnxx/dfnxx ( 3 x 3 ) mechanical data
ld39100xx, ld39100xx12, ld39100xx25 package mechanical data doc id 15676 rev 3 21/23 figure 35. dfn6 (3 x 3) footprint recommended data
revision history ld39100xx, ld39100xx12, ld39100xx25 22/23 doc id 15676 rev 3 8 revision history table 8. document revision history date revision changes 29-jul-2009 1 initial release. 16-apr-2010 2 modified figure 8 on page 10 . 11-oct-2011 3 document stat us promoted from prelim inary data to datasheet.
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